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| Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Document order number: MC33888 Rev 3.0, 10/2004 Product Preview Quad High-Side and Octal Low-Side Switch for Automotive The 33888 is a single-package combination of a power die with four discrete high-side MOSFETs (two 10 m and two 40 m) and an integrated IC control die consisting of eight low-side drivers (600 m each) with appropriate control, protection, and diagnostic features. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each high-side output has its own parallel input for pulse-width modulation (PWM) control if desired. The low sides share a single configurable direct input. The 33888 is available in two power packages. Features * Dual 10 m High Side, Dual 40 m High Side, Octal 600 m Low Side * Full Operating Voltage of 6.0 V to 27 V * SPI Control of High-Side Overcurrent Limit, High Side Current Sense, Output OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout * SPI Reporting of Program Status and Fault * High-Side Analog Current Feedback with Selectable Ratio * Enhanced 16 V Reverse Polarity VPWR Protection 33888 33888A SOLID STATE RELAY FOR AUTOMOTIVE APPLICATIONS Freescale Semiconductor, Inc... Bottom View PNB SUFFIX APNB SUFFIX CASE 1438-06 36-TERMINAL PQFN (12 x 12) Top View FB SUFFIX CASE 1315-03 64-TERMINAL PQFP ORDERING INFORMATION Device PC33888PNB/R2 PC33888APNB/R2 MC33888FB/R2 -40C to 125C Temperature Range (TA) Package 36 PQFN 64 PQFP 33888 Simplified Application Diagram VPWR +5.0 V +5.0 V 8 x Relay or LED 33888 4 MCU A/D A/D VPWR FS VDD IHS0:IHS3 LS4:LS11 ILS RST SPI HS3 WDIN HS2 CSNS2-3 HS1 CSNS0-1 HS0 FSI GND Loads 4 This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 1. Features Comparison: 33888 and 33888A Parameter Undervoltage Low-Side Output Shutdown Low-Side Drain-to-Source ON Resistance Symbol VPWRUV RDS(ON) Condition - VPWR = 4.5 V; VDD = 3.5 V Extended Mode, VDD = 3.4 V 33888 5.0 V Not specified 33888A 3.0 V 8.0 For details, see page 11 14 Recommended Frequency of SPI Operation f SPI Not specified 2.1 MHz (max) 17 VDD VPWR Freescale Semiconductor, Inc... VIC IUP CS SCLK IDWN SO SI RST WAKE FS IN0 IN1 IN2 IN3 ILS SPI 3.0 MHz Internal Regulator Over/Undervoltage Protection 10 m Gate Driver Selectable Current Limit Open Load HS0 Detection Logic Overtemperature Detection HS0 CSNS0-1 HS1 Gate Control and Fault 10 m HS1 Selectable Output Current Recopy (Analog MUX) Gate Control and Fault 40 m RDWN IDWN HS2 Selectable Output Current Recopy (Analog MUX) HS2 CSNS2-3 Gate Control and Fault 40 m HS3 VIC HS3 WDIN Watchdog Gate Control Clamp Overtemperature ILIM Open Load x8 FSI LS4 LS5 LS6 LS7 LS8 LS9 LS10 LS11 GND Figure 1. 33888 Simplified Internal Block Diagram 33888 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Transparent Top View of Package VPWR 2 LS11 LS10 GND GND VDD LS9 LS8 LS7 LS6 LS5 LS4 SO FS 1 36 35 WDIN FSI RST WAKE GND IHS1 IHS0 CSNS0-1 34 33 32 31 30 29 28 HS2 14 CS SCLK SI ILS GND IHS3 16 17 18 19 20 21 22 23 13 12 11 10 9 8 7 6 5 4 3 15 GND (Control Die) Freescale Semiconductor, Inc... IHS2 CSNS2-3 Internally Connected to VPWR 24 VPWR (Power Die) 25 HS3 26 HS1 27 HS0 TERMINAL DEFINITIONS FOR PQFN Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 19. Terminal 1 Terminal Name FS Formal Name Fault Status (Active Low) Positive Power Supply Low-Side Output 4 Low-Side Output 6 Low-Side Output 8 Low-Side Output 10 Ground Low-Side Output 5 Low-Side Output 7 Low-Side Output 9 Low-Side Output 11 Digital Drain Voltage (Power) Definition This output terminal is an open drain indication that goes active low when a fault mode is detected by the device. Specific device fault indication is given via the SO terminal. These terminal connects to the positive power supply and are the source input of operational power for the device. Each low-side terminal is one 0.6 low-side output MOSFET drain, which pulls current through the connected loads. Each of the outputs is actively clamped at 53 V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 500 mA. These terminals serve as the ground for the source of the low-side output transistors as well as the logic portion of the device. Each low-side terminal is one 0.6 low-side output MOSFET drain, which pulls current through the connected loads. Each of the outputs is actively clamped at 53 V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 800 mA. This is an external input terminal used to supply power to the SPI circuit. 2, 24 3 6 8 10 4, 11, 15, 20, 32 5 7 9 12 13 VPWR LS4 LS6 LS8 LS10 GND LS5 LS7 LS9 LS11 VDD MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 3 Freescale Semiconductor, Inc. TERMINAL DEFINITIONS FOR PQFN (continued) Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 19. Terminal 14 Terminal Name SO Formal Name Serial Output Definition This is an output terminal connected to the SPI Serial Data Input terminal of the MCU or to the SI terminal of the next device in a daisy chain. This output will remain tri-stated unless the device is selected by a low CS terminal. The output signal generated will have CMOS logic levels and the output data will transition on the rising edges of SCLK. The serial output data provides fault information for each output and is returned MSB first when the device is addressed. OD11 through OD0 are output fault bits for outputs 11 through 0, respectively. This is an input terminal connected to a chip select output of a microcontroller (MCU). This IC controls which device is addressed (selected) by pulling the CS terminal of the desired device logic Low, enabling the SPI communication with the device, while other devices on the serial link keep their serial outputs tri-stated. This input has an internal active pullup and requires CMOS logic levels. This input terminal is connected to the SCLK terminal of the master MCU, which is a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an operating frequency, fSPI, and is idle between command transfers. It is 50% duty cycle and has CMOS logic levels. This signal is used to shift data to and from the 33888. This input terminal is connected to the SPI Serial Data Output terminal of the MCU from which it receives output command data. This input has an internal active pull-down and requires CMOS logic levels. The serial data transmitted on this line is a 16-bit control command sent MSB first, which controls the twelve output channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure that data is available on the falling edge of SCLK. This input terminal is used to directly control a number of the low-side devices as configured by SPI. This terminal may or may not be activated depending on the configured state of the internal logic. Each high-side input terminal is used to directly control only one designated highside output. These inputs may or may not be activated depending on the configured state of the internal logic. These terminals deliver a ratioed amount of the high-side output current that can be used to generate signal ground referenced output voltages for use by the MCU. Each respective CSNS terminal can be configured via SPI to deliver current from either of the two assigned outputs, or the currents could be the sum of the two. Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or HS3 are sensed via CSNS2-3. Each terminal is the source of a 40 m MOSFET high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS terminals depending on the internal configuration. These outputs are current limited and thermally protected. During fail-safe mode, output HS2 will be turned on until the device is reinitialized and then immediately followed by normal operation. Each terminal is the source of a 10 m MOSFET high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS terminals depending on the internal configuration. These outputs are current limited and thermally protected. During fail-safe mode, output HS0 will be turned on until the device is reinitialized and then immediately followed by normal operation. This terminal is used to input a logic [1] signal in order to enable the watchdog timer function. An internal clamp protects the terminal from high voltages when current is limited with an external resistor. This input has a passive internal pulldown. 16 CS Chip Select (Active Low) Freescale Semiconductor, Inc... 17 SCLK Serial Clock 18 SI Serial Input 19 ILS Low-Side Input 21 22 30 31 23 29 IHS3 IHS2 IHS0 IHS1 CSNS2-3 CSNS0-1 High-Side Input 3 High-Side Input 2 High-Side Input 0 High-Side Input 1 Current Sense 2-3 Current Sense 0-1 25 28 HS3 HS2 High-Side Output 3 High-Side Output 2 26 27 HS1 HS0 High-Side Output 1 High-Side Output 0 33 WAKE Wake 33888 4 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. TERMINAL DEFINITIONS FOR PQFN (continued) Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 19. Terminal 34 Terminal Name RST Formal Name Reset (Active Low) Definition This input terminal is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode. This terminal also starts the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal should not be allowed to be at logic [1] until VDD is in regulation. This input has an internal passive pulldown. The Fail-Safe input terminal level determines the state of the outputs after a watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state. If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be disabled, thus allowing operation without a watchdog signal. This input terminal is a CMOS logic level input that is used to monitor system operation. If the incoming watchdog signal does not transition within the normal watchdog timeout range, the device will operate in the Fail-Safe mode. This input has an active internal pulldown. 35 FSI Fail-Safe Input Freescale Semiconductor, Inc... 36 WDIN Watchdog Input MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 5 Freescale Semiconductor, Inc. WAKE IHS1 IHS0 CSNS0-1 VPWR 64 63 62 61 60 59 58 57 56 55 54 53 VPWR HS2 HS2 NC NC NC RST FSI WDIN Freescale Semiconductor, Inc... 1 2 FS 3 VPWR 4 LS4 5 GND 6 LS5 7 LS6 8 GND 9 LS7 10 LS8 11 GND 12 LS9 13 LS10 14 GND 15 LS11 16 VDD 17 SO 18 CS 19 SCLK 20 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC NC NC HS0 HS0 HS0 HS0 HS0 HS0 HS0 HS1 HS1 HS1 HS1 HS1 HS1 HS1 NC NC NC TERMINAL DEFINITIONS FOR PQFP Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 19. Terminal 1 Terminal Name FSI Formal Name Fail-Safe Input Definition The Fail-Safe input terminal level determines the state of the outputs after a watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state. If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be disabled, thus allowing operation without a watchdog signal. This input terminal is a CMOS logic level input that is used to monitor system operation. If the incoming watchdog signal does not transition within the normal watchdog timeout range, the device will operate in the Fail-Safe mode. This input has an active internal pulldown. This output terminal is an open drain indication that goes active low when a fault mode is detected by the device. Specific device fault indication is given via the SO terminal. These terminal connects to the positive power supply and are the source input of operational power for the device. Each low-side terminal is one 0.6 low-side output MOSFET drain, which pulls current through the connected loads. Each of the outputs is actively clamped at 53 V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 500 mA. These terminals serve as the ground for the source of the low-side output transistors as well as the logic portion of the device. 2 WDIN Watchdog Input 3 FS Fault Status (Active Low) Positive Power Supply Low-Side Output 4 Low-Side Output 6 Low-Side Output 8 Low-Side Output 10 Ground 4, 26, 27, 58, 59 5 8 11 14 6, 9, 12, 15 VPWR LS4 LS6 LS8 LS10 GND 33888 6 SI 21 ILS 22 IHS3 23 IHS2 24 CSNS2-3 25 VPWR 26 For More Information On This Product, Go to: www.freescale.com VPWR 27 HS3 28 HS3 29 NC 30 NC 31 NC 32 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. TERMINAL DEFINITIONS FOR PQFP (continued) Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 19. Terminal 7 10 13 16 17 18 Terminal Name LS5 LS7 LS9 LS11 VDD SO Formal Name Low-Side Output 5 Low-Side Output 7 Low-Side Output 9 Low-Side Output 11 Digital Drain Voltage (Power) Serial Output Definition Each low-side terminal is one 0.6 low-side output MOSFET drain, which pulls current through the connected loads. Each of the outputs is actively clamped at 53 V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 800 mA. This is an external input terminal used to supply power to the SPI circuit. This is an output terminal connected to the SPI Serial Data Input terminal of the MCU or to the SI terminal of the next device in a daisy chain. This output will remain tri-stated unless the device is selected by a low CS terminal. The output signal generated will have CMOS logic levels and the output data will transition on the rising edges of SCLK. The serial output data provides fault information for each output and is returned MSB first when the device is addressed. OD11 through OD0 are output fault bits for outputs 11 through 0, respectively. This is an input terminal connected to a chip select output of a microcontroller (MCU). This IC controls which device is addressed (selected) by pulling the CS terminal of the desired device logic Low, enabling the SPI communication with the device, while other devices on the serial link keep their serial outputs tri-stated. This input has an internal active pullup and requires CMOS logic levels. This input terminal is connected to the SCLK terminal of the master MCU, which is a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an operating frequency, fSPI, and is idle between command transfers. It is 50% duty cycle and has CMOS logic levels. This signal is used to shift data to and from the 33888. This input terminal is connected to the SPI Serial Data Output terminal of the MCU from which it receives output command data. This input has an internal active pull-down and requires CMOS logic levels. The serial data transmitted on this line is a 16-bit control command sent MSB first, which controls the twelve output channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure that data is available on the falling edge of SCLK. This input terminal is used to directly control a number of the low-side devices as configured by SPI. This terminal may or may not be activated depending on the configured state of the internal logic. Each high-side input terminal is used to directly control only one designated highside output. These inputs may or may not be activated depending on the configured state of the internal logic. These terminals deliver a ratioed amount of the high-side output current that can be used to generate signal ground referenced output voltages for use by the MCU. Each respective CSNS terminal can be configured via SPI to deliver current from either of the two assigned outputs, or the currents could be the sum of the two. Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or HS3 are sensed via CSNS2-3. Each terminal is the source of a 40 m MOSFET high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS terminals depending on the internal configuration. These outputs are current limited and thermally protected. During fail-safe mode, output HS2 will be turned on until the device is reinitialized and then immediately followed by normal operation. These terminals are not connected internally. Freescale Semiconductor, Inc... 19 CS Chip Select (Active Low) 20 SCLK Serial Clock 21 SI Serial Input 22 ILS Low-Side Input 23 24 61 62 25 60 IHS3 IHS2 IHS0 IHS1 CSNS2-3 CSNS0-1 High-Side Input 3 High-Side Input 2 High-Side Input 0 High-Side Input 1 Current Sense 2-3 Current Sense 0-1 28, 29 56, 57 HS3 HS2 High-Side Output 3 High-Side Output 2 30-35, 50-55 NC Not Connected MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 7 Freescale Semiconductor, Inc. TERMINAL DEFINITIONS FOR PQFP (continued) Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 19. Terminal 36-42 43-49 Terminal Name HS1 HS0 Formal Name High-Side Output 1 High-Side Output 0 Definition Each terminal is the source of a 10 m MOSFET high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS terminals depending on the internal configuration. These outputs are current limited and thermally protected. During fail-safe mode, output HS0 will be turned on until the device is reinitialized and then immediately followed by normal operation. This terminal is used to input a logic [1] signal in order to enable the watchdog timer function. An internal clamp protects the terminal from high voltages when current is limited with an external resistor. This input has a passive internal pulldown. This input terminal is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode. This terminal also starts the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal should not be allowed to be at logic [1] until VDD is in regulation. This input has an internal passive pulldown. 63 WAKE Wake Freescale Semiconductor, Inc... 64 RST Reset (Active Low) 33888 8 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit ELECTRICAL RATINGS Power Supply Voltage Steady State Input Terminal Voltage (Note 1) WAKE Input Terminal Clamp Current Continuous per Output Current (Note 2) Low-Sides 4, 6, 8, 10 Low-Sides 5, 7, 9, 11 VIN IWICI IOUTLS 500 800 IOUTHS 10 5.0 mJ EHS EHS ELS VESD1 VESD2 450 120 50 V 2000 200 A VPWR -16 to 41 -0.3 to 7.0 2.5 V mA mA V Freescale Semiconductor, Inc... Continuous per Output Current (Note 3) High-Sides 0, 1 High-Sides 2, 3 Output Clamp Energy High-Sides 0, 1 (Note 4) High-Sides 2, 3 (Note 5) Low-Sides (Note 6) ESD Voltage Human Body Model (Note 7) Machine Model (Note 8) Notes 1. Exceeding voltage limits on SCLK, SI, CS, WDIN, RST, IHS, FSI, or ILS terminals may cause a malfunction or permanent damage to the device. 2. Continuous low-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125C ambient temperature will require calculation of maximum output current using package thermal resistance. 3. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125C ambient temperature will require calculation of maximum output current using package thermal resistance. 4. Active HS0 and HS1 clamp energy using the following conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 40 mH, TJ = 150C. 5. 6. 7. 8. Active HS2 and HS3 clamp energy using the following conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 10 mH, TJ = 150C. Active low-side clamp energy using the following conditions: single nonrepetitive pulse, 450 mA, TJ = 150C. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 9 Freescale Semiconductor, Inc. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Control Die Thermal Resistance (Note 9) PQFP One Low-Side ON Two Low-Side ON 12.5 9.3 7.3 5.9 3.2 8.6 6.0 4.6 3.8 2.0 RPJC 0.5 0.15 0.5 0.1 RJA 33 37 TSOLDER 225 240 C/W C/W TA TJ TSTG RCJC -40 to 125 -40 to 150 -55 to 150 C C/W C Freescale Semiconductor, Inc... Three Low-Side ON Four Low Side ON All Low-Sides ON PQFN One Low-Side ON Two Low-Side ON Three Low-Side ON Four Low Side ON All Low-Sides ON Power Die Thermal Resistance (Note 9) PQFP One High-Side 2, 3 ON All High-Sides ON PQFN One High-Side 2, 3 ON All High-Sides ON Thermal Resistance, Junction to Ambient, Natural Convection, Four-Layer Board (Note 9) PQFP PQFN Peak Terminal Reflow Temperature During Solder Mounting (Note 10) PQFP PQFN Notes 9. 10. C Board dimensions are 8.0 cm x 8.0 cm x 1.5 mm with a 300 mm2 copper area on the bottom layer. Terminal soldering temperature limit is 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 33888 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER INPUT Supply Voltage Range Fully Operational VPWR Supply Current TJ > 125C TJ 125C IPWR(ON) - - IPWR(SBY) - - IPWR(SS) - - VDD IDD(ON) - - IDD(SS) ISLK(SS) - - VPWROV VPWROV(HYS) VPWRUV VPWRUV 3.0 5.0 VPWRUV(HYS) 0.1 4.0 5.6 0.3 4.4 6.0 0.5 V 28.5 0.2 5.0 - - 32 0.6 5.6 3.0 1.0 36 1.5 6.0 V V V V - 4.2 2.9 - 7.0 5.0 5.0 A A 4.5 - 1.0 5.0 80 25 5.5 V mA 4.2 2.9 7.0 5.0 A 17 - 25 20 mA VPWR 6.0 - 27 mA V Freescale Semiconductor, Inc... VPWR Standby Current (All Outputs OFF, Open Load Detection Disabled, WAKE = H, RST = H) TJ > 125C TJ 125C Sleep State Supply Current (VPWR < 12.6 V, RST < 0.5 V, WAKE < 0.5 V, HS[0:3] = 0 V) (Note 11) TJ = 85C TJ = 25C Logic Supply Voltage Range Logic Supply Current TJ > 125C TJ 125C Logic Supply Sleep State Current Sleep State Low-Side Output Leakage Current (per Low-Side Output, RST = LOW) TJ = 85C TJ = 25C Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis Undervoltage High-Side Output Shutdown (Note 12) Undervoltage Low-Side Output Shutdown APNB Suffix Only (Note 12) PNB and FB Suffixes Undervoltage High-Side Shutdown Hysteresis Notes 11. This parameter is tested at 125C with a maximum value of 10 A. 12. SPI/IO and internal logic operational. Outputs will recover in instructed state when VPWR voltage level returns to normal as long as the level does not go below VPWRUV. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 11 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER INPUT (continued) Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) CSNS0-1/HS0, CSNS0-1/HS1 Current Sense Ratio (CSR[0:1] ) Accuracy HS[0:1] Output Current 1.0 A 2.0 A 5.0 A -35 -19 -14 -12 -12 CSR - CSR[2:3]_ACC -30 -19 -13.5 -12 -9.0 VSENSE 4.5 6.0 7.0 - - - - - 30 19 13.5 12 9.0 V 1/880 - % - - - - - 35 19 14 12 12 - CSR[0:1]_ACC CSR[0:1] - 1/1400 - % - Freescale Semiconductor, Inc... 6.5 A 10 A Current Sense Ratio (VPWR = 9.0 V - 16 V, CSNS < 4.5 V) CSNS2-3/HS2, CSNS2-3/HS3 Current Sense Ratio (CSR[2:3] ) Accuracy HS[2:3] Output Current 0.5 A 1.0 A 3.0 A 3.7 A 5.0 A Current Sense Clamp Voltage ICNS = 15 mA Generated by the Device HS0 AND HS1 POWER OUTPUTS Drain-to-Source ON Resistance (IOUT = 5.5 A) TJ = 25C VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V TJ = 150C VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V Reverse Battery Source-to-Drain ON Resistance (IOUT = -5.5 A, TJ = 25C) VPWR = -12 V Output Self-Limiting Peak Current Outputs ON, VOUT = VPWR -2.0 V Output Self-Limiting Sustain Current Outputs ON, VOUT = VPWR -2.0 V Open Load Detection Current (Note 13) IOLDC ILIM(SUS) 13 30 25 - 34 100 A ILIM(PK) 33 49 66 A RDS(ON)REV - - 0.02 A - - - - - - 0.034 0.017 0.017 - - - - - - 0.02 0.01 0.01 RDS(ON) Notes 13. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 33888 12 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit HS0 AND HS1 POWER OUTPUTS (continued) Output Fault Detection Threshold (Note 14) Output Programmed OFF Output Negative Clamp Voltage 0.5 A < IOUT < 2.0 A, Output OFF Overtemperature Shutdown (Outputs OFF) (Note 15) Overtemperature Shutdown Hysteresis (Note 15) TSD TSD(HYS) VCL -20 160 10 - 175 - - 190 30 C C VOFD(THRES) 2.0 3.0 4.0 V V Freescale Semiconductor, Inc... HS2 AND HS3 POWER OUTPUTS Drain-to-Source ON Resistance (IOUT = 4.5 A) TJ = 25C VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V TJ = 150C VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V Reverse Battery Source-to-Drain ON Resistance (IOUT = 4.5 A, TJ = 25C) VPWR = -12 V Output Self-Limiting Peak Current Outputs ON, VOUT = VPWR -2.0 V Output Self-Limiting Sustain Current Outputs ON, VOUT = VPWR -2.0 V Open Load Detection Current (Note 16) Output Fault Detection Threshold (Note 17) Outputs Programmed OFF Output Negative Clamp Voltage 0.5 A < IOUT < 2.0 A, Outputs OFF Overtemperature Shutdown (Outputs OFF) (Note 18) Overtemperature Shutdown Hysteresis (Note 18) TSD TSD(HYS) VCL -20 160 10 - 170 - - 190 30 C C IOLDC VOFD(THRES) 2.0 3.0 4.0 V ILIM(SUS) 6.0 25 10 - 15 100 A V ILIM(PK) 15 23 35 A RDS(ON)REV - - 0.08 A - - - - - - 0.136 0.068 0.068 - - - - - - 0.08 0.04 0.04 RDS(ON) Notes 14. Output fault detection threshold with outputs programmed OFF. For the Low-Side Outputs, fault detection thresholds are the same for output open and battery shorts. 15. Guaranteed by design. Not production tested. 16. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 17. Output fault detection threshold with outputs programmed OFF. 18. Guaranteed by design. Not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 13 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit LOW-SIDE POWER OUTPUTS Drain-to-Source ON Resistance (IOUT = 0.3 A) TJ = 25C VPWR = 4.5 V; VDD = 3.5 V, 33888A Only VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V TJ = 150C VPWR = 4.5 V; VDD = 3.5 V, 33888A Only VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V Output Self-Limiting Current (Outputs Programmed ON, VOUT = 3.0 V) Low-Side 4, 6, 8, 10 Low-Side 5, 7, 9, 11 Output OFF Open Load Detection Current (Note 19) Output Programmed OFF, VOUT = 3.0 V Output Fault Detection Threshold (Note 20) Output Programmed OFF Output Clamp Voltage 2.0 mA < IOUT < 200 mA, Outputs OFF Low-Side Body Diode Voltage (I = -300 mA, TJ = 125C) Overtemperature Shutdown (Outputs OFF) (Note 21) Overtemperature Shutdown Hysteresis (Note 21) VBD TLIM TLIM(HYS) VCL 41 0.5 160 10 53 0.7 170 20 60 0.9 190 30 V C C VOFD(THRES) 2.0 3.0 4.0 V IOLDC 25 50 100 V ILIM 0.5 0.8 0.9 1.3 1.5 2.0 A - - - - - - - - - - - - - - - - 8.0 1.0 0.7 0.6 8.0 1.8 1.1 0.9 A RDS(ON) Freescale Semiconductor, Inc... Notes 19. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 20. Output fault detection threshold with outputs programmed OFF. For the low-side outputs, fault detection thresholds are the same for output open and battery shorts. 21. Guaranteed by design. Not production tested. 33888 14 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CONTROL INTERFACE Input Logic High Voltage (Note 22) Input Logic Low Voltage (Note 22) Input Logic Voltage Hysteresis (SI, CS, SCLK, IHS[0:3], ILS) (Note 23) Input Logic Pulldown Current (SI, SCLK, IHS[0:3], ILS, WDIN) Input Logic Pulldown Resistor (WAKE, RST) VIH VIL VIN(HYS) IDWN RDWN IUPC IUPF VWIC VWIF VSOH VSOL ISOLK CIN CSO 0.7 VDD - 100 5.0 100 5.0 5.0 7.0 -2.0 0.8 VDD - -5.0 - - - - 350 - 200 - - - - - 0.2 0 4.0 - - 1.0 750 20 400 20 20 14 -0.3 - 0.4 5.0 12 20 V V mV A k A A V V V V A pF pF Freescale Semiconductor, Inc... Input Logic Pullup Current (CS, VIN = 0.7 VDD) (Note 24) Input Logic Pullup Current (FSI, VIN = 3.5 V) Wake Input Clamp Voltage (IWICI < 2.5 mA) (Note 25) Wake Input Forward Voltage (IWICI = -2.5 mA) SO High-State Output Voltage (IOH = 1.0 mA) FS, SO Low-State Output Voltage (IOL = -1.6 mA) SO Tri-State Leakage Current (CS 3.5 V) Input Capacitance (Note 26) SO, FS Tri-State Capacitance (Note 23) Notes 22. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN input signals. The WAKE, FSI, and RST signals are derived from an internal supply. 23. Parameter is guaranteed by design but is not production tested. 24. CS is pulled up to VDD. 25. 26. The current must be limited by a series resistor when using voltages higher than the WICV. Input capacitance of SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN. This parameter is guaranteed by process monitoring but is not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 15 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT TIMING High-Side Output Rising Fast Slew Rate (Note 27) 6.0 V < VPWR < 9.0 V 9.0 V < VPWR < 16 V 16 V < VPWR < 27 V High-Side Output Rising Slow Slew Rate (Note 28) 6.0 V < VPWR < 9.0 V 9.0 V < VPWR < 16 V 16 V < VPWR < 27 V High-Side Output Falling Fast Slew Rate (Note 27) 6.0 V < VPWR < 9.0 V 9.0 V < VPWR < 16 V 16 V < VPWR < 27 V High-Side Output Falling Slow Slew Rate (Note 28) 6.0 V < VPWR < 9.0 V 9.0 V < VPWR < 16 V 16 V < VPWR < 27 V High-Side Output Turn ON Delay Time (Note 29) High-Side Output Turn OFF Delay Time (Note 30) Low-Side Output Falling Slew Rate (Note 31) Low-Side Output Rising Slew Rate (Note 31) Low-Side Output Turn ON Delay Time (Note 32) Low-Side Output Turn OFF Delay Time (Note 33) Low-Side Output Fault Delay Timer (Note 34) Watchdog Timeout (Note 35) SRF_SLOW 0.05 0.08 0.08 - 0.15 - 30 80 3.0 6.0 2.0 4.0 150 584 0.3 0.4 0.5 150 150 10 20 10 10 250 770 s s V/s V/s s s s ms SRF_FAST 0.2 0.3 0.5 - 0.8 - 1.0 1.5 2.2 V/s SRR_SLOW 0.01 0.01 0.01 - 0.08 - 0.14 0.18 0.2 V/s SRR_FAST 0.03 0.05 0.1 - 0.5 - 0.6 0.8 1.1 V/s V/s Freescale Semiconductor, Inc... t DLY(ON) t DLY(OFF) SRF SRR 5.0 5.0 0.5 1.0 0.5 0.5 70 340 t DLY(ON) t DLY(OFF) t DLY(FS) t WDTO Notes 27. High-side output rise and fall fast slew rates measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR -3.0 V (see Figure 2, page 18). These parameters are guaranteed by process monitoring. 28. High-side output rise and fall slow slew rates measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR -3.0 V (see Figure 2, page 18). These parameters are guaranteed by process monitoring. 29. High-side output turn-ON delay time measured from 50% of the rising IHS to 0.5 V of output OFF with RL = 27 resistive load (see Figure 2, page 18). 30. High-side output turn-OFF delay time measured from 50% of the falling IHS to VPWR -2.0 V of the output OFF with RL = 27 resistive load (see Figure 2, page 18). 31. Low-side output rise and fall slew rates measured across a 5.0 resistive load at low-side output = 10% to 90% (see Figure 3, page 18). 32. Low-side output turn-ON delay time measured from 50% of the rising ILS to 90% of VOUT with RL = 27 resistive load (see Figure 3, page 18). 33. Low-side output turn-OFF delay time measured from 50% of the falling ILS to 10% of VOUT with RL = 27 resistive load (see Figure 3, page 18). These parameters are guaranteed by process monitoring. 34. Propagation time of Short Fault Disable Report Delay measured from rising edge of CS to output disabled, low-side = 5.0 V, and device configured for low-side output overcurrent latchoff using CLOCCR. 35. Watchdog timeout delay is measured from the rising edge of WAKE or RST from the sleep state to the HS[0:1] turn-ON with the outputs driven OFF and the FSI floating. The accuracy of t WDTO is maintained for all configured watchdog timeouts. 33888 16 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT TIMING (continued) Peak Current Limit Timer (Note 36) Direct Input Switching Frequency (Note 37) t PCT f PWM 40 - 70 125 100 - ms Hz SPI INTERFACE TIMING (Note 38) Recommended Frequency of SPI Operation Normal Mode Extended Mode: VDD = 3.4 V; VPWR = 4.5 V, APNB Suffix Only f SPI - - - - 50 - - 50 - - 50 25 25 3.0 2.1 167 300 5.0 167 167 167 167 83 83 MHz Freescale Semiconductor, Inc... Required Low State Duration for RST (Note 39) Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 40) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 40) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 40) Required High State Duration of SCLK (Required Setup Time) (Note 40) Required Low State Duration of SCLK (Required Setup Time) (Note 40) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 40) SI to Falling Edge of SCLK (Required Setup Time) (Note 40) Falling Edge of SCLK to SI (Required Hold Time) (Note 40) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (Note 41) SI, CS, SCLK, Incoming Signal Fall Time (Note 41) Time from Falling Edge of CS to SO Low Impedance (Note 42) Time from Rising Edge of CS to SO High Impedance (Note 43) Time from Rising Edge of SCLK to SO Data Valid (Note 44) 0.2 VDD SO 0.8 VDD, CL = 200 pF t WRST t CS t ENBL t LEAD t WSCLKh t WSCLKl t LAG t SI(SU) t SI(HOLD) t RSO - - - - - - - - - ns ns s ns ns ns ns ns ns ns - 25 50 ns t FSO - 25 - - - 65 50 50 50 145 145 t RSI t FSI t SO(EN) t SO(DIS) t VALID - - - - ns ns ns ns ns - 65 105 Notes 36. t PCT measured from the rising edge of CS to 90% of ILIMPKHS[x,x] when the peak current limit is enabled. 37. 38. 39. 40. 41. 42. 43. 44. This frequency is a typical value. Maximum switching frequencies are dictated by the turn-ON delay, turn-OFF delay, output rise and fall times, and the maximum allowable junction temperature. Symmetrical 50% duty cycle SCLK clock period of 333 ns. RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33888 is the minimum guaranteed time needed from the MCU. Rise and fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 k pullup on CS. Time required for output status data to be terminated at SO. 1.0 k pullup on CS. Time required to obtain valid data out from SO following the rise of SCLK. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 17 Freescale Semiconductor, Inc. Timing Diagrams Direct input or spi bit Direct Input or SPI Bit VPWR VPWR VPWR - 0.5V VPWR -0.5 V VPWR - V VPWR -3.0 3V SRR_SLOW SRr_slow SRF_SLOW SRf_slow SRF_FAST SRf_fast SRR_FAST SRr_fast Freescale Semiconductor, Inc... 0.5 V 0.5V t DLY(ON) Tdly(on) Tdly(off) t DLY(OFF) Figure 2. Output Slew Rates and Time Delays, High Side Direct input or SPI Bit Direct Input or SPI bit PWR VPWR 90% 90% V SRf SRF SRr SRR 10% 10% t DLY(ON) Tdly(on) Tdly(off) t DLY(OFF) Figure 3. Output Slew Rates and Time Delays, Low Side 33888 18 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION This 33888 is a single-package combination of a power die with four discrete high-side MOSFETs and an integrated IC control die consisting of eight low-side drivers with appropriate control, protection, and diagnostic features. The high-side drivers are useful for both internal and external vehicle lighting applications as well as capable of driving inductive solenoid loads. The low-side drivers are capable of controlling lowcurrent on/off type inductive loads, such as relays and solenoids as well as LED indicators and small lamps (see simplified application diagram, page 2). The device is useful in body control, instrumentation, and other high-power switching applications and systems. The 33888 is available in two packages: a power-enhanced 12 x 12 nonleaded Power QFN package with exposed tabs and a 64-lead Power QFP plastic package. Both packages are intended to be soldered directly onto the printed circuit board. The 33888 differs from the 33888A as explained in Table 1, page 2. Freescale Semiconductor, Inc... FUNCTIONAL DESCRIPTION SPI Interface and Protocol Description The SPI interface has full duplex, three-wire synchronous data transfer and has four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI/SO terminals of the 33888 follow a first-in first-out (D15/D0) protocol with both input and output words transferring the most significant bit first. All inputs are compatible with 5.0 V CMOS logic levels. During SPI output control, a logic [0] in a message word will result in the designated output being turned off. Similarly, a logic [1] will turn on a corresponding output. The SPI lines perform the following functions: Serial Clock (SCLK) The SCLK terminal clocks the internal shift registers of the 33888. The serial input (SI) terminal accepts data into the input shift register on the falling edge of the SCLK signal while the serial output terminal (SO) shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK terminal be in a logic [0] state whenever the chip select (CS) makes any transition. For this reason, it is recommended that the SCLK terminal be kept in a logic [0] state as long as the device is not accessed (CS in logic [1] state). SCLK has an active internal pulldown, IDWN. When CS is logic [1], signals at the SCLK and SI terminals are ignored and SO is tri-stated (high impedance). (See Figures 4 and 5 on page 20.) Serial Interface (SI) This is a serial interface (SI) command data input terminal. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI terminal, starting with D15 to D0. The 12 outputs of the 33888 are configured and controlled using the 3-bit addressing scheme and the 12 assigned data bits designed into the 33888. SI has an active internal pulldown, IDWN. Serial Output (SO) The SO data terminal is a tri-stateable output from the shift register. The SO terminal remains in a high-impedance state until the CS terminal is put into a logic [0] state. The SO data report the status of the outputs as well as provide the capability to reflect the state of the direct inputs. The SO terminal changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. When an output is ON or OFF and not faulted, the corresponding SO bit, OD11:OD0, is a logic [0]. If the output is faulted, the corresponding SO state is a logic [1]. SO OD14:OD12 reflect the state of six various inputs (three at a time) depending upon the reported state of the previously written watchdog bit OD15. Chip Select (CS) The CS terminal enables communication with the master microcontroller (MCU). When this terminal is in a logic [0] state, the 33888 is capable of transferring information to and receiving information from the MCU. The 33888 latches in data from the input shift registers to the addressed registers on the rising edge of CS. The 33888 transfers status information from the power outputs to the shift registers on the falling edge of CS. The output driver on the SO terminal is enabled when CS is logic [0]. CS is only transitioned from a logic [1] state to a logic [0] state when SCLK is a logic [0]. CS has an active internal pullup, IUP. The 33888 is capable of communicating directly with the MCU via the 16-bit SPI protocol as described in the next section. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 19 Freescale Semiconductor, Inc. CSB CS SCLK SI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SO OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 Freescale Semiconductor, Inc... Notes 1. RST is in a logic [1] state during the above operation. 2. D15:D0 relate to the most recent ordered entry of program data into the 33888. 3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888. Figure 4. Single 16-Bit Word SPI Communication CS CSB SCLK SI D15 D14 D13 D2 D1 D0 D15* D14* D13* D2* D1* D0* SO OD15 OD14 OD13 OD2 OD1 OD0 D15 D14 D13 D2 D1 D0 Notes 1. RST is a logic [1] state during the above operation. 2. D15:D0 relate to the most recent ordered entry of program data into the 33888. 3. D15*:D0* relate to the first 16 bits of ordered entry data out of the 33888. 4. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888. Figure 5. Multiple 16-Bit Word SPI Communication Serial Input Communication SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB, D15, and ending with the LSB, D0 (refer to Table 2, page 21). Each incoming command message on the SI terminal can be interpreted using the following bit assignments: the first twelve LSBs, D11:D0, control each of the twelve outputs; the next three bits, D14:D12, determine the command mode; and the MSB, D15, is the watchdog bit. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 33888 has six registers that are used to configure the device and control the state of the four high-side and eight low-side outputs (Table 3, page 21). The registers are addressed via D14:D12 of the incoming SPI word (Table 2, page 21). 33888 20 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. . Table 2. SI Message Bit Assignment Bit Sig MSB SI Msg Bit D15 D14:12 D11 D10 D9 D8 D7 Message Bit Description Watchdog in: toggled to satisfy watchdog requirements. Register address bits. Used to configure Low-Side Output LS11. Used to configure Low-Side Output LS10. Used to configure Low-Side Output LS9. Used to configure Low-Side Output LS8. Used to configure Low-Side Output LS7. Used to configure Low-Side Output LS6. LSB D3 D2 D1 D0 D4 Table 2. SI Message Bit Assignment (continued) Bit Sig SI Msg Bit D5 Message Bit Description Used to configure Low-Side Output LS5 (Watchdog timeout MSB during WDCSCR configuration). Used to configure Low-Side Output LS4 (Watchdog timeout LSB during WDCSCR configuration). Used to configure High-Side Output HS3. Used to configure High-Side Output HS2. Used to configure High-Side Output HS1. Used to configure High-Side Output HS0. Freescale Semiconductor, Inc... D6 Table 3. Serial Input Address and Configuration Bit Map SI Register SOCR DICR LFCR WDCSCR OLCR CLOCCR NOT USED TEST WD D15 x x x x x x x x D14 0 1 0 1 0 1 0 1 Address D13 0 0 1 1 0 0 1 1 D12 0 0 0 0 1 1 1 1 D11 LS11 D10 LS10 D9 LS9 Low-Side D8 LS8 PWB8 D7 LS7 PWB7 D6 LS6 PWB6 D5 LS5 PWB5 D4 LS4 PWB4 D3 HS3 PWB3 High-Side D2 HS2 PWB2 D1 HS1 PWB1 D0 HS0 PWB0 PWB11 PWB10 PWB9 A/OB11 A/OB10 A/OB9 A/OB8 A/OB7 A/OB6 A/OB5 A/OB4 A/OB3 A/OB2 A/OB1 A/OB0 NA OL11 OC11 - - NA OL10 OC10 - - NA OL9 OC9 - - NA OL8 OC8 - - NA OL7 OC7 - - NA OL6 OC6 - - WDH OL5 OC5 - - WDL OL4 OC4 - - CS3 OLB3 ILIM3 - ILIMPK CS2 OLB2 ILIM2 - WD CS1 OLB1 ILIM1 - ILIM CS0 OLB0 ILIM0 - OT x=Don't care. NA=Not applicable. Device Register Addressing The following section describes the possible register addresses and their impact on device operation. Address 000--SPI Output Control Register (SOCR) The SOCR register allows the MCU to control the outputs via the SPI. Incoming message bits D3:D0 reflect the desired states of high-side outputs HS3:HS0. Message bits D11:D4 reflect the desired state of low-side outputs LS11:LS4, respectively. Address 100--Direct Input Control Register (DICR) The DICR register is used by the MCU to enable direct input control of the outputs. For the outputs, a logic [0] on bits D11:D0 will enable the corresponding output for direct control. A logic [1] on a D11:D0 bit will disable the output from direct control. Address 010--Logic Function Control Register (LFCR) The LFCR register is used by the MCU to configure the relationship between SOCR bits D11:D0 and the direct inputs IHS[0:3] and ILS. While addressing this register (if the direct inputs were enabled for direct control with the DICR), a logic [1] on any or all of the D3:D0 bits will result in a Boolean AND of the IHS[0:3] terminal(s) with its (their) corresponding D3:D0 message bit(s) when addressing the SOCR. A logic [1] on any or all of the D11:D4 bits will result in a Boolean AND of the ILS and the corresponding D11:D4 message bits when addressing the SOCR. Similarly, a logic [0] on the D3:D0 bits will result in a Boolean OR of the IHS[0:3] terminal(s) with their corresponding message bits when addressing the SOCR register, and the ILS will be Boolean ORed with message bits D11:D4 when addressing the SOCR register (if ILS is enabled). MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 21 Freescale Semiconductor, Inc. Address 110--Watchdog and Current Sense Configuration Register (WDCSCR) The WDCSCR register is used by the MCU to configure the watchdog timeout and the CSNS0-1 and CSNS2-3 terminals. The watchdog timeout is configured using bits D4 and D5. The state of D4 and D5 determine the divided value of the WDTO. For example, if D5 and D4 are logic [0] and logic [0], respectively, then the WDTO will be in the default state as specified in Table 3, page 21. A D5 and a D4 of logic [0] and logic [1] will result in a watchdog timeout of WDTO / 2. Similarly, a D5 and a D4 of logic [1] and logic [0] result in a watchdog timeout of WDTO / 4, and a D5 and a D4 of logic [1] and logic [1] result in a watchdog timeout of WDTO / 8. Note that when D5 and D4 bits are programmed for the desired watchdog timeout period, the WD bit (D15) should be toggled as well to ensure that the new timeout period is programmed at the beginning of a new count sequence. CSNS0-1 is the current sense output for the HS0 and HS1 outputs. Similarly, the CSNS2-3 terminal is the current sense output for the HS2 and HS3 outputs. In this mode, a logic [1] on any or all of the message bits that control the high-side outputs will result in the sensed current from the corresponding output being directed out of the appropriate CSNS output. For example, if D1 and D0 are both logic [1], then the sensed current from HS0 and HS1 will be summed into the CSNS0-1. If D2 is logic [1] and D3 is logic [0], then only the sensed current from HS2 will be directed out of CSNS2-3. Address 001--Open Load Configuration Register (OLCR) The OLCR register allows the MCU to configure each of the outputs for open load fault detection. While in this mode, a logic [1] on any of the D3:D0 message bits will disable the corresponding outputs' circuitry that allows the device to detect open load faults while the output is OFF. For the low-side drivers, a logic [1] on any of the D11:D4 bits will enable the open load detection circuitry. This feature allows the MCU to minimize load current in some applications and may be useful to diagnose output shorts to battery (for HS). Address 101--Current Limit Overcurrent Configuration Register (CLOCCR) The CLOCCR register allows the MCU to individually override the peak current limit levels for each of the high-side outputs. A logic [1] on any or all of the D3:D0 bit(s) results in the corresponding HS3:HS0 output terminals to current limit at the sustain current limit level. This register also allows the MCU to enable or disable the overcurrent shutdown of the low-side output terminals. A logic [1] on any or all of the D11:D4 message bit(s) will result in the corresponding LS11:LS4 terminals latching off if the current exceeds ILIM after a timeout of t DLY(FS). Address 011--Not Used Not currently used. Address 111--TEST The TEST register is reserved for test and is not accessible via SPI during normal operation. Freescale Semiconductor, Inc... Serial Output Communication (Devise Status Return Data) When the CS terminal is pulled low, the output status register for each output is loaded into the output register and the fault data is clocked out MSB (OD15) first as the new message data is clocked into the SI terminal. OD15 reflects the state of the watchdog bit (D15) that was addressed during the prior SOCR communication (refer to Table 4, page 23). If bit OD15 is logic [0], then the three MSBs OD14:OD12 will reflect the logic states of the IHS0, IHS1, and FSI terminals, respectively. If bit OD15 is logic [1], then the same three MSB bits will reflect the logic states of the IHS2, IHS3, and WAKE terminals. The next twelve bits clocked out of SO following a low transition of the CS terminal (OD11:OD0) will reflect the state of each output, with a logic [1] in any of the bits indicating that the respective output experienced a fault condition prior to the CS transition. Any bits clocked out of the SO terminal after the first 16 will be representative of the initial message bits that were clocked into the SI terminal since the CS terminal first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification. Following a CS transition logic [0] to logic [1], the device determines if the message was of a valid length (a valid message length is one that is a multiple of 16 bits) and if so, latches the data into the appropriate registers. At this time, the SO terminal is tri-stated and the fault status register is now able to accept new fault status information. 33888 22 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Table 4. Serial Output Bit Assignment Bit Sig MSB SO Msg Bit OD15 OD14 Message Bit Description Reflects the state of the Watchdog bit from the previously clocked-in message. If OD15 is logic [0], then this bit will reflect the state of the direct input IHS0. If OD15 is logic [1], then this bit will reflect the state of IHS2. If OD15 is logic [0], then this bit will reflect the state of the direct input IHS1. If OD15 is logic [1], then this bit will reflect the state of IHS3. If OD15 is logic [0], then this bit will reflect the state of the input FSI. If OD15 is logic [1], then this bit will reflect the state of the input WAKE. Reports the absence or presence of a fault on LS11. Reports the absence or presence of a fault on LS10. Table 4. Serial Output Bit Assignment (continued) Bit Sig SO Msg Bit OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 LSB OD0 Message Bit Description Reports the absence or presence of a fault on LS9. Reports the absence or presence of a fault on LS8. Reports the absence or presence of a fault on LS7. Reports the absence or presence of a fault on LS6. Reports the absence or presence of a fault on LS5. Reports the absence or presence of a fault on LS4. Reports the absence or presence of a fault on HS3. Reports the absence or presence of a fault on HS2. Reports the absence or presence of a fault on HS1. Reports the absence or presence of a fault on HS0. OD13 OD12 Freescale Semiconductor, Inc... OD11 OD10 MODES OF OPERATION Watchdog and Fail-Safe Operation The watchdog is enabled and a timeout is started when the WAKE or RST transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series limiting resistance that limits the internal clamp current. The timeout is a multiple of an internal oscillator. As long as the WDIN terminal or the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout, WDTO (or a divided value configured during a WDCSCR message), then the device will operate normally. If the watchdog timeout occurs before the WD bit or the WDIN terminal is toggled, then the device will revert to a Fail-Safe mode until the device is reinitialized (if the FSI terminal is left disconnected). During Fail-Safe mode, all outputs will be OFF except for HS0 and HS2, which will be driven ON regardless of the state of the various direct inputs and modes (Table 5). The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST terminals from logic [1] to logic [0]. In the event the WAKE terminal was not transitioned to a logic [1] during normal operation and the watchdog times out, then the device can be brought out of fail-safe by bringing the RST to a logic [0]. If the FSI terminal is tied to GND, then the watchdog, and therefore fail-safe operation, will be disabled. Table 5. Fail-Safe Operation and Transitions to Other 33888 Modes WAKE RST WDTO HS0 HS2 0 1 0 0 x NO OFF OFF OFF OFF LS[4:11], HS[1,3] OFF OFF Comments Device in Sleep mode. All outputs are OFF. When RST transitions to logic [1], device is in default. Fail-Safe mode. Device reset into Default mode by transitioning WAKE to logic [0]. Device in Normal operating mode. Fail-Safe mode. Device reset into Default mode by transitioning RST to logic [0]. Device in Normal operating mode. Fail-Safe mode. Device reset into Default mode by transitioning RST and WAKE to logic [0]. 1 0 YES ON ON OFF 0 0 1 1 NO YES S ON S ON S OFF 1 1 1 1 NO YES S ON S ON S OFF Assumptions: Normal operating voltage and junction temperatures, FSI terminal floating. x=Don't care. S=State determined by SPI and/or direct input configurations. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 23 Freescale Semiconductor, Inc. Default Mode The default mode describes the state of the device after first applying VPWR voltage or a reset transition from logic [0] to logic [1] prior to SPI communication. In the default mode, all outputs will be off (assuming that the direct inputs ILS and IHS[0:3] and the WAKE terminal are at logic [0]). All of the specific terminal functions will operate as though all of the addressable configuration register bits were set to logic [0]. This means, for example, that all of the low-side outputs will be controllable by the ILS terminal, and that all high-side outputs will be controllable via their respective IHS terminals. During the default mode, all high-side drivers will default with open load detection enabled. All low-side drivers will default with open load detection disabled. This mode allows limited control of the 33888 with the direct inputs in the absence of an SPI. Overtemperature Fault The 33888 incorporates overtemperature detection and shutdown circuitry into each individual output structure. Overtemperature detection occurs when an output is in the ON state. When an output is shut down due to an overtemperature condition, no other output is affected. The output experiencing the fault is shut down to protect itself from damage. A fault bit is loaded into the status register if the overtemperature condition is removed, and the fault bit is cleared upon the rising edge of CS. Freescale Semiconductor, Inc... Returning the device to the default state after a period of normal operation, followed by the removal of the VPWR voltage, requires that the RST input be held at a logic [0] state until VPWR falls to a level below 2.0 V. If the RST and VDD input levels are normal, then failure to allow VPWR to fall below 2.0 V will result in an internal bias circuit clamping the VPWR terminal to approximately 3.5 V. Once VPWR falls below 2.0 V, the RST can be returned to 5.0 V without re-enabling the bias circuit. For the low-side outputs, the faulted output is latched OFF during an overtemperature condition. If the temperature falls below the recovery level, TLIM(HYS), then the output can be turned back ON only after the output has first been commanded OFF either through the SPI or the ILS, depending on the logic configuration. For the high-side output(s), an overtemperature condition will result in the output(s) turning OFF until the temperature falls below the TLIM(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut the output(s) OFF. Overvoltage Fault The 33888 shuts down all outputs during an overvoltage condition on the VPWR terminal. The outputs remain in the OFF state until the overvoltage condition is removed. Fault status for all outputs is latched into the status register. Following an overvoltage condition, the next write cycle sent by the SO terminal of the 33888 is logic [1] on OD11:OD0, indicating all outputs have shut down. If the overvoltage condition is removed, the status register can be cleared by a rising edge on CS. Fault Logic Requirements The 33888 indicates all of the following faults as they occur: * * * * Overtemperature Fault Overvoltage Fault Open Load Fault Overcurrent Fault With the exception of the overvoltage, these faults are output specific. The overvoltage fault is a global fault. The overcurrent fault is only reported for the low-side outputs. The 33888 low-side outputs incorporate an internal fault filter, t DLY(FS). The fault timer filters noise and switching transients for overcurrent faults when the output is ON and open load faults when the output is OFF. All faults are latched and indicated by a logic [1] for each output in the 33888 status word (Table 4, page 23). If the fault is removed, the status bit for the faulted output will be cleared by a rising edge on CS. The FS terminal is driven to a logic [0] when a fault exists on any of the outputs. FS provides real time monitoring of the overvoltage fault. For the high-side outputs, FS provides real time monitoring of the open load and overtemperature. For the low-side outputs, the FS is latched to a logic [0] for open load, overtemperature, and overcurrent faults. The latch is cleared by toggling the state of the faulted output or by bringing RST low. Open Load Fault The 33888 incorporates open load detection circuitry on every output. A high-side or low-side output open load fault is detected and reported as a fault condition when the corresponding output is disabled (OFF) if it was configured for open load detection by setting the appropriate bit to logic [0] (HS3:HS0) or logic [1] (LS11:LS4) in the OLFCR register (Figure 6, page 25). The high-side open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn off the output. If the open load fault is removed or if the faulted output is commanded ON, the status register can be cleared by a rising edge on CS. Note that the device default state will enable the high-side open load detection and disable the low-side open load detection circuits, respectively. 33888 24 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. 33888 LOW = Logic 0 MOSFET 50 mA VPWR RL OUT VPWR RL OUTPUT + - VTHRES VOFD(THRES)LS 2.0 V-4.0 V Figure 6. Low-Side Output OFF Open Load Detection Freescale Semiconductor, Inc... Overcurrent Fault Requirements: Low-Side Output An overcurrent condition is defined as any current value greater than ILIM (500 mA minimum value for LS5, LS7, LS9, LS11, and 800 mA minimum value for LS4, LS6, LS8, LS10). The status of the corresponding bit in the CLOCCR register determines whether a specific output shuts down or continues to operate in an analog current limited mode until either the overcurrent condition is removed or the thermal shutdown limit is reached (Figure 7, page 26). If the overcurrent shutdown mode is disabled, the fault reporting is disabled as well. For the low-side output of interest, if a D11:D4 bit was set to a logic [1] in the OLCR register, the overcurrent protection shutdown circuitry will be enabled for that output. When a lowside output is commanded ON either from the SPI or the ILS terminal, the drain of the low-side driver will be monitored for a voltage greater than the fault detection threshold (3.0 V typical). If the drain voltage exceeds this threshold, a timer will start and the output will be turned off and a fault latched in the status register after the timeout expires. The faulted output can be retried only by commanding the output OFF and back ON either through the SPI or the ILS terminal, depending on the logic configuration. If the fault is gone, the retried output will return to normal operation and the status register can be cleared on a rising edge of CS. If the fault remains, the retried output will latch off after the fault timer expires and the fault bit will remain set in the status register. For the low-side output of interest, if a D11:D4 bit was set to a logic [0] in the OLCR register, the output experiencing an overcurrent condition is not disabled until an overtemperature fault threshold has been reached. The specific output goes into an analog current limit mode of operation, ILIM. The 33888 uses overtemperature shutdown to protect all outputs in this mode of operation. If the overcurrent condition is removed before the output has reached its overtemperature limit, the output will function as if no fault has occurred. Note that each pair of low-side drivers, LS4:LS5, LS6:LS7, LS8:LS9, and LS10:LS11, consists of a 500 mA and a 800 mA output. Each pair of outputs shares ground bondwires. The bondwires are not rated to handle both outputs in current limit mode simultaneously. Overcurrent Fault Requirements: High-Side Output For the high-side output of interest, the output current is limited to one of four levels depending on the type of high-side output, the amount of time that has elapsed since the output was switched on, and the state of the CLOCCR register. Assuming that bits D3:D0 of the CLOCCR register are at logic [0], the current limit levels of the outputs will be initially at their peak levels as specified by the ILIM(PK)HS[0:3]. After the high-side output is switched on, the peak current timer starts. After a period of time t PCT, the current limit level changes to the sustain levels ILIMSUSHS[x,x]. For the high-side output of interest, if a D3:D0 bit of the CLOCCR is at logic [1], then the assigned output will only current limit at the sustain level specified by ILIMSUSHS[x,x]. Current is limited until the overtemperature circuitry shuts OFF the device. The device turns ON automatically when the temperature fails below the TLIM(HYS). This cycle continues indefinitely until action is taken by the master to shut the output(s) OFF. Reverse Battery Requirements The low-side and high-side outputs survive the application of reverse battery as low as -16 V. Ground Disconnect Protection In the event that the 33888 ground is disconnected from load ground, the device protects itself and safely turns OFF the outputs, regardless of the state of the output at the time of disconnection. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 25 Freescale Semiconductor, Inc. 33888 HIGH = Fault MOSFET ON VPWR RL OUT + Digital - + Analog - VREF VOFD(THRES)LS 2.0 V-4.0 V Freescale Semiconductor, Inc... VTHRES Figure 7. Low-Side Short Circuit Detection and Analog Current Limit Undervoltage Shutdown Requirements All outputs turn off at some battery voltage below 6.0 V; For the A version, the low side shutdown at a lower value, VPWRUV. however, as long as the level stays above 5.0 V, the internal logic states within the device are designed to be sustained. This ensures that when the battery level then rises above 6.0 V, the device will return to the state that it was in prior to the excursion between 5.0 V and 6.0 V (assuming that there was no SPI communication or direct input changes during the event). If the battery voltage falls to a level below 5.0 V, then the internal logic is reinitialized and the device is then in the default state upon the return of levels in excess of 6.0 V. Output Voltage Clamping Each output has an internal clamp to provide protection and dissipate the energy stored in inductive loads. Each clamp independently limits the drain-to-source voltage to the range specified in the Power Outputs section of the STATIC ELECTRICAL CHARACTERISTICS table beginning on page 12. Also see Figure 8. Drain-Source Clamp Voltage (VCL = 53 V) Drain Current (ID = 0.5 A) Drain-Source ON Voltage (VDS(ON)) Current Area (IA) GND Drain Voltage Clamp Energy (EJ = IA x VCL x t) VPWR Time Figure 8. Low-Side Output Voltage Clamping 33888 26 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. PACKAGE INFORMATION Soldering Information The 33888 is packaged in a surface mount power package intended to be soldered directly onto the printed circuit board. The device was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows: * Convection: 225C +5.0C/-0C * Vapor Phase Reflow (VPR): 215C to 219C * Infrared (IR)/Convection: 225C +5.0C/-0C The maximum peak temperature during the soldering process should not exceed 230C. The time at maximum temperature should range from 10 seconds to 40 seconds maximum. APPLICATIONS Freescale Semiconductor, Inc... Typical Application Figure 9 shows a typical application for the 33888. VPWR +5.0 V 10 k 4 FS +5.0 V VDD 8 x Relay or LED 33888 VPWR VDD MCU A/D A/D 4 IHS0:IHS3 ILS RST SPI WDIN CSNS2-3 CSNS0-1 FSI GND 8 x 0.5 Loads 40 m 40 m 10 m 10 m 65 W 65 W 21 W 5.0 W 21 W 5.0 W RC2 RC1 Figure 9. 33888 Typical Application Diagram MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 27 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS PNB SUFFIX APNB SUFFIX 36-TERMINAL PQFN NONLEADED PACKAGE CASE 1438-06 ISSUE E (Top View) 12 14 16 1 36 A 0.1 C M Freescale Semiconductor, Inc... PIN 1 INDEX AREA 12 23 29 25 28 M B 2X 0.1 C PIN NUMBER REFERENCE ONLY 0.1 C 2.2 2.20 2.0 1.95 DETAIL G 0.05 C 4 0.05 0.00 7.3 6.9 0.1 A B C 2X 4.05 C SEATING PLANE DETAIL G 30X 10X 1.60 1.35 0.62 0.48 0.1 0.05 M M CAB C 6 1.20 10X 0.95 36 2 PLACES 0.4 1 13X 4X 14 16 0.8 0.90 0.65 0.40.2 2.875 15 6 7X 0.8 X0.50.2 1 5 0.1 A B C 1.45 1.05 3.85 3.45 0.1 A B C NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. 5. METAL PADS CONNECTED TO THE GND. 6. MINIMUM METAL GAP SHOULD BE 0.25MM. 3 0.6 1.25 6X 1.00 29 23 24 1.625 2X 4.45 4.05 0.1 A B C 2.8 2.3 28 27 26 25 4X (0.25) (2X 1.25) 0.5 (2X 0.75) (0.05) 2X 0.2 0.0 4X 2.0 1.5 2X (2X 0.5) (2X 0.75) 2X 2.2 1.8 0.1 M 0.05 M CAB C (0.3) 3.75 8.70 8.30 0.1 A B C 11.7 11.3 0.1 A B C 2.95 2.55 0.1 M C A B 0.05 M C VIEW M-M (Bottom View) CASE 1438-06 ISSUE E MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888 28 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FB SUFFIX 64-TERMINAL PQFP PLASTIC PACKAGE CASE 1315-03 ISSUE B 4 E1 PIN ONE ID A 53 h 64 6 2X E2 h D4 1 52 58X D3 e Freescale Semiconductor, Inc... E3 D1 D2 4 2X D bbb M C B BOTTOM VIEW e/2 b c 33 20 c1 b1 B 6 21 4X e1 E bbb M 32 SECTION W-W NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DIMENSIONS "D1" AND "E1" DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.15 PER SIDE. DIMENSION "D1" AND "E1" DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 5. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-. MILLIMETERS MIN MAX --3.15 --0.25 2.5 2.9 0 0.1 0.8 1 16.95 17.45 13.9 14.1 12.5 12.9 9.3 9.7 13.4 13.6 16.95 17.45 13.9 14.1 2.35 2.65 9.3 9.7 0.8 1.1 0.22 0.38 0.22 0.33 0.23 0.32 0.23 0.29 0.65 BSC 2.925 BSC --0.8 0 7 0.12 0.2 0.1 CA DETAIL Y 3 A A2 64X H DATUM PLANE C SEATING PLANE 5 b M aaa CAB A4 DIM A A1 A2 A3 A4 D D1 D2 D3 D4 E E1 E2 E3 L b b1 c c1 e e1 h aaa bbb ccc E3 W GAUGE PLANE 0.35 ccc W A1 L (1.6) A3 DETAIL Y MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 29 Freescale Semiconductor, Inc. NOTES Freescale Semiconductor, Inc... 33888 30 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. NOTES Freescale Semiconductor, Inc... MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33888 31 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors For More Information On This Product, Go to: www.freescale.com MC33888 |
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